1. Field of the Invention
The present invention generally relates to a sense amplifier and method that allows pipelined read, restore and write operations.
2. Description of the Related Art
In fast page asynchronous DRAMs, the column access cycle time is limited by the column address access path. As a result, improvements are limited by the column address access time. EDO (Extended Data Out) DRAMs use a pipelined operation for the address and data paths, allowing faster hyper-column cycle time. Synchronous DRAMs (SDRAMs) utilize an internal burst counter to increment the address, which further improves the column burst cycle time. This improvement limits the column access cycle time to the rate at which data is transferred from the main sense amplifier to the data output circuit. In order to improve the column access/cycle time, it is important to perform successive read, write, and restore operations. However, this is difficult due to data congestion on global data lines and read-write data busses.
FIG. 9 shows a block diagram of the column access path of an illustrative memory circuit. The memory chip comprises a memory array 13 connected over bitlines (BLt and BLc) to a plurality of first sense amplifiers 14, which are connected to multiplexor 16 and connected over global data lines, MDQt and MDQc, to the second sense amplifier 24. In a read mode, the first sense amplifiers 14 amplify a charge from the memory cell in the memory array 13 and transfer the information in the form of a small differential signal (0.1V to 0.3V) through the multiplexor 16 to the second sense amplifier 24. A specific column address determines which data is transferred. The transfer of information is initiated with a column select latch (CSL) signal, which opens at least one MUX 16. The second sense amplifier 24 translates the small differential signal to a higher level to be transferred to and out of the package (I/O) by the off chip driver/receiver 28. In a write mode, the off chip driver/receiver 28 transfers data to be written from the I/O to the second sense amplifier 24. The second sense amplifier 24 transfers a large differential signal over the global data lines, MDQt and MDQc, through the multiplexor 16 to a specific first sense amplifier 14 (determined by the column address) to be written into the memory cell of the memory array 13. Again, the transfer of information is initiated with a column select latch (CSL) signal, which opens at least one MUX 16.
FIG. 6 shows a prior art sense amplifier that includes some of the problems discussed above. In particular, the read, restore (precharge), and write operations are performed separately or discretely in time. This type of sense amplifier does not permit overlapping of successive read operations, restore operations, write operations, or combinations of read/restore/write operations and accordingly results in a slower operation.
First, a read and restore operation will be discussed. The equalization signal EQLn rises to logic `1` to terminate restoration and equalization of the true and complement global data buses MDQt and MDQc, respectively. To perform a read operation, the sense amplifier switch signal SSASWn at gates of the transistors P4 and P5 switches to logic `0` to transfer data on the global data buses MDQt/MDQc into the sense amplifier. Subsequently, the sense amplifier enable signal SSAE at the gate of transistor N3 switches to logic `1` to amplify and latch the transferred data. The input signal DRVn to the NOR gates I1 and I2 then switches to logic `0` to send the amplified data to the gates of the output transistors N4 and N5. Since either of the transistors N4 or N5 conducts (depending on the state of the data), the amplified data value is placed on the differential buses RWDt and RWDc. The sense amplifier enable signal SSAE at the gate of the transistor N3 then switches to logic `0` to terminate the read operation. The equalization signal EQLn switches to a logic `0`, the global data buses MDQt and MDQc are restored and equalized to a logic `1` and the sense amplifier nodes GDt and GDc are equalized. The next read or write operation can occur.
The sense amplifier switch signal SSASWn and the DRVn signal are logic `1` and sense amplifier enable signal SSAE is logic `0` to disable the sense amplifier. The equalization signal EQLn rises to logic `1` to terminate restoration and equalization of the global data buses MDQc and MDQt. To perform a write operation, the write gate signal WGTn then falls to logic `0`. For a write `0` operation, the RWDt signal will be logic `0` and the RWDc signal will be logic `1`. This causes the gate of the transistor N6 to be logic `1`. The transistor N6 will conduct and pull the global data bus MDQt down to logic `0`. The gate of the transistor P10 will be at logic `0`. The transistor P6 will conduct and pull the global data bus up to logic `1`. For a write `1` operation, the RWDt signal will be logic `1` and the RWDc signal will be logic `0`. This causes the gate of the transistor P9 to be logic `0`. The transistor P9 will conduct and pull the global data bus MDQt up to logic `1`. The gate of transistor N7 will be at logic `1`. The transistor N7 will conduct and pull the global data bus MDQc down to logic `0`. The write gate signal WGTn then rises to logic `1` to terminate the write operation. Subsequently, the equalization signal EQLn switches to a logic `0` and the global data buses MDQt and MDQc are restored and equalized to a logic `1`.
Since the restoring and the equalization of the global data lines MDQt and MDQc and internal sense amplifier nodes GDt and GDc are controlled by the same signal (i.e., the equalization signal EQLn), the read and restore operations cannot be overlapped and thus the read, write or restore modes cannot be executed simultaneously. FIGS. 7 and 8 show the timing of the respective signals during each of the read, write and restore operations. As can be clearly seen from these Figs.s, the different operations cannot be overlapped and thus the prior art sense amplifier cannot operate in a pipelined manner. This limits further improvements to the column access time. A further disadvantage is that the prior art sense amplifiers use differential busses RWDt and RWDc that swing from 0V to the on-chip uplevel of Vint. Since these lines are heavily loaded, this requires a large amount of current to charge and discharge the signal lines.